1. Field of the Invention
The present invention relates generally to protection devices, and, more particularly, to protection devices for protecting integrated circuits from various electrical transients, including electrostatic discharge (ESD).
2. Description of the Related Art
As very large scale integration (VLSI) circuit geometries continue to shrink, the decrease in the corresponding gate oxide thicknesses, relative to breakdown voltage, have resulted in the device's greater susceptibility to damage from application of excessive voltages, for example, by an electrostatic discharge (ESD) event. In particular, during an ESD event, charge is transferred between one or more pins of the integrated circuit and another conducting object in a time period that is typically less than one microsecond. As indicated above, this charge transfer can generate voltages that are large enough to break down insulating films (e.g., gate oxides) on the device or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.
Accordingly, many attempts have been made in the prior art to protect semiconductor devices, with particular attention to the problem of protecting field effect devices from such ESD events. FIG. 1 is representative of a common approach taken in the prior art to protect integrated circuit devices. An input protection scheme indicated generally at 10, for protecting an input buffer 12 from ESD events occurring at input pad 14 includes a primary ESD protection circuit 16, a secondary ESD protection circuit 18, and a core clamp 20 for providing power supply ESD protection. Protection circuits, such as 10, are usually connected to all I/O pads of an integrated circuit to safely dissipate the energy associated with ESD events without causing any damage to internal circuitry, such as input buffer 12, that is connected to I/O pad 14. The double diode primary ESD circuit 16 includes diodes D.sub.1, and D.sub.2 and is connected between a positive power supply bus V.sub.DD and a negative power supply bus V.sub.SS, with the input pad 14 being connected at a node common to the diodes. The primary ESD circuit 16 carries the majority of the charge during an ESD event. In particular, diode D.sub.1 shunts ESD charge to the V.sub.SS bus when the polarity is negative, while diode D.sub.2 shunts ESD charge to the V.sub.DD bus when the polarity is positive. Secondary ESD protection circuit 18 includes a resistor R in series with a grounded gate FET clamp M.sub.0, which is operative to limit the voltage across the gate oxides of input buffer 12. The amount of charge that flows through secondary ESD protection circuit 18 is relatively small in comparison to the amount of charge flowing through primary ESD protection circuit 16. Core clamp 20 permits charge to be transferred between the power supply busses during an ESD event.
Although protection circuitry 10 provides satisfactory performance relative to ESD events on input pins, the performance of circuitry 10 does not meet state-of-the-art standards for so-called input "leakage" currents in certain applications. In particular, contemporary VLSI circuit designs provide for instances where the input pins on the integrated circuit are subjected to voltages which exceed the positive power supply voltage of the integrated circuit. For example, particular integrated circuits may provide for operation in a mixed-voltage environment where the integrated circuit may operate at one voltage level (e.g., V.sub.DD =3.3 volts), but must interface with another integrated circuit operating at a different, higher, power supply voltage (e.g., 5.0 volts). As another example, input pins on a programmable integrated circuit, particularly those pins associated with programming of the device, may need to tolerate voltages well above the power supply voltage to effect programming due to various and well known solid state mechanisms that require such high voltage (e.g., hot carrier injection, tunneling, and dielectric breakdown). Moreover, other integrated circuits may provide for an additional logic level by using a voltage level above the power supply voltage level, as may be required to control special test modes for product characterization, control programming, or other functions that are not part of normal operation.
Referring again to FIG. 1, it should be appreciated that when the input voltage applied to input pad 14 exceeds the positive power supply V.sub.DD by more than the forward-biased diode voltage drop of about 0.7 volts, diode D.sub.2 will begin to conduct. Particularly, when the input pad is at 5 volts, and the positive power supply voltage V.sub.DD is at 3.3 volts, the voltage drop across diode D.sub.2 will cause D.sub.2 to become strongly forward-biased, resulting in an excessive level of input current--the so-called input "leakage" current. This condition is undesirable, and, in many applications, commercially unacceptable. It should be understood that secondary ESD protection circuit 18 neither clamps the input voltage, nor carries any appreciable leakage current when input voltages on input pad 14 rise above V.sub.DD during normal operation. Thus, an acceptable solution to this problems lies in addressing the primary ESD protection circuit 16.
One approach taken in the art in remedying the above-identified leakage current problem uses a grounded gate FET as the primary ESD protection. The grounded gate FET is a field effect transistor having its drain terminal connected to the input pad, while its gate and source terminals are "tied" to the negative power supply bus V.sub.SS. Another approach uses a field FET, which is a field effect transistor having both gate and drain terminals connected to the input pad, and having its source terminal connected to V.sub.SS. Although both the grounded gate FET and the field FET eliminated the leakage path to V.sub.DD, ESD performance was unsatisfactory. In particular, due to the use of silicided diffusions, uniform current flow, and thus consistent ESD results were difficult to ensure in these types of structures because they rely on a so-called snapback mechanism to dissipate discharge. A third approach proposed in the art employs a so-called diode stack; that is, several series-connected diodes (e.g., five) substituted for the single diode D.sub.2. This approach has also proven unsatisfactory under worst-case conditions, insofar as the input leakage current was found to be unacceptably large. This large current was due to Darlington amplification resulting from the parasitic PNP bipolar transistors formed by each of the diodes in the stack between the input pad and the positive power supply bus V.sub.DD.
Accordingly, there is a need to provide an improved ESD protection circuit suitable for use in an integrated circuit, that minimizes or eliminates one or more of the problems as set forth above.